EEL 6167 - VLSI Design
Fall, 2007
| Faculty | : | Dr. Subbarao Wunnava, Professor, P.E. |
| Office | : | EC 3912 |
| Office Hours | : | 2.00 PM – 4.00 PM T&R |
| Phone | : | 305-348-3018 |
| : | subbara@fiu.edu | |
| Classroom | : | EC 2420 |
| Class Time | : | 12.30-13.45 T&R |
Suggested Text Books
“Introduction to VLSI Circuits and Systems”
by Dr. John Uyemura, John Wiley & Sons,
Latest Edition, 2004
Suggested References and Sites
Motorola Web site www.motorola.com
Cypress Web site www.cypress.com
Intel Web site www.intel.com
Mentor graphics at www.mentor.com
Wayne Wolf “Modem VLSI” 2nd edition, prentice Hall, 2004
Michael Vai “VLSI Design” CRC Press, 2003
VLSI Supplemental material: Subbarao Wunnava Fall 2004
Course Objective
To learn about the recent trends in the Software Driven Hardware
Description Languages (HDL)s; and implement the appropriate system designs;
and study the system level behavior of the Very Large Scale Integrated Circuit
(VLSI) realizations. Specific design layout and the methodologies, the litho
graphic schemes will also be discussed. Also fault tolerant, thermal management
and layout optimization for VLSI will be introduced. Industry oriented projects
will be discussed with emphasis on VLSI realizations
Course Organization
Negotiations are under way with Microelectronics and VLSI consortium and the Industry for obtaining the VLSI design
platforms and the associated software capabilities. Nearly half of the course time will be devoted for the practical VLSI
design schemes from the top level system to the MOS transistor level.
Course Grade
| 2 Tests | 40% |
| Homework and Projects | 30% |
| Pop Quizzes (Unanounced) | 30% |
It is the departmental policy not to make up any of the missed examinations. The grade distribution, as per the
departmental guide lines is as follows:
| A | A- | B+ | B | B- |
| >94% | >90% | >86% | >82% | >78% |
Design Course Content
General concepts of VLSI
Nature of the semiconductors, doping concepts
The P and N type configurations for MOS
General MOS FET configurations and Characteristics
Case studies
2. Designing with the CMOS at the system and transistor level
Correspondence between the gate properties
Transmission Gate circuits and implementations
The layout correspondence
3. Introduction to the VLSI materials and properties
The RLC properties and schemes
The timing considerations
The FET arrays and designs
4. Fabrication of the CMOS VLSI circuits
The process flow and the lithography
The MOSFET sizing and layout criteria
Case studies
5. Analysis and Design of the CMOS suited for VLSI
Gate Design and the transient analysis
The Spice and other CAD platforms
The BiCOMS drivers and layouts
Case studies
6. VLSI system specifications with the HDL
RTL modeling with the Verilog & VHDL
Switch Level Modeling
Case studies
7. General VLSI sub system designs
Modular designs
Integrated designs
ASIC implementations
8. Industry standard VLSI design schemes and analysis
Reliable design schemes
Timing and error analysis
Classes Day & Date Topic Details
1-4 08/28 T Introduction Chap 1: History of VLSI
08/30 R VLSI concepts & Electronics Reliability concepts: Assn HW1&2
09/04 T General structure of VLSI circuits
09/06 R MOS Switches & Gates Chap 2 & Notes
Complex CMOS gating structures Plan for Project 1
Data flow control in VLSI
5-8 09/11 T Transmission Gating in VLSI Chap 2: HW12 Due
09/13 R Flip Flop Structures Assign Project 1 & HW 34
09/18 T General Circuit configurations Discussion on Project 1
09/20 R General Circuit Layouts Notes and Handouts
9-12 09/25 T Time for Project 1
09/27 R CMOS Layers Chp 3 & 4
10/02 T Design of CMOS arrays Notes & Handouts, Chps 3&4
10/04 R Industry Standard CMOS arrays Notes and Handouts, HW 3&4 Due
13-16 10/09 T Stick Diagrams Chap 3 & 4 & Notes
10/11 R Fabrication of CMOS Chapter 5
10/16 T Test1 Chaps 1 - 5
10/18 R Problems in CMOS layouts Chapters 5 & 6, Assign HW 5&6
17-20 10/23 T FET Active Region properties Chps 5 &6
10/25 R Mixed mode operations Notes & Chp 7
10/30 T Project 1 Due Discussions on Project 1
11/01 R Problems in VLSI Designs Notes, Handouts; HW 5&6 Due
21-24 11/06 T Problems in VLSI designs Chps 6,7 &8
11/08 R Oscillations and uncertainties Assign Project 2
11/13 T Physical Limitations of VLSI Discussions on Project 2
11/15 R Verilog & VHDL based VLSI Chp 9 & 10
25-28 11/20 T Verilog & VHDL based VLSI Chps 9 & 10, Notes
11/22 R Time for Project 2
11/27 T VLSI Power Optimizations & SOC Discussion on Proj 2
11/29 W TEST 2 Comprehensive
29-30 12/04 M Project 2 Due: Project Presentations
12/06 W Project Presentations Discussions
Unannounced Quizzes will be given during the course